Qwenputer: a developer compiled a RISC-V CPU into Qwen3.5-4B's weights, with no training, and says it runs 18 million instructions without an error

Qwenputer is an experiment by developer Divyansh Agrawal that puts a working computer inside a language model. In a blog post dated October 22, 2026, which reached the Hacker News front page on October 29, he describes taking Alibaba's open-weight Qwen3.5-4B and adding a 32-bit RISC-V CPU as extra layers whose weights were calculated by a compiler, not learned. Qwen can then hand the CPU a calculation through an ordinary tool call and get an exact answer back, with no external tool or Python process involved. It is related to, but different from, the looped-transformer ideas covered in our explainer on OpenAI's loop transformers.

This story is based on Agrawal's post, the Qwenputer GitHub repository and its RISC-V design document, the Qwenputer model card on Hugging Face, Qwen's Qwen3.5-4B model card, and the published papers linked below, checked October 29, 2026. Every claim about how Qwenputer works or performs is Agrawal's; no outside group has published a replication.

The short version

• What was built: Qwen3.5-4B plus a RISC-V CPU implementing the RV32IM instruction set, with the Zba extension and a small big-number unit. The CPU takes up 11 layers in front of Qwen's 32.
• How: "there's no training involved: a compiler sets every weight directly," Agrawal writes. Qwen's original weights "stay exactly as they are."
• Memory: registers and RAM are stored in the running state of Qwen3.5's Gated DeltaNet layers, not in its weights.
• Claimed results: passes the official riscv-tests, matches the qemu emulator, and "has run 18 million instructions free-running without a single error."
• Limits, per the author: an 18.8 GB checkpoint, a custom driver, slow big calculations and no operating-system support.

What is Qwenputer?

It's a modified Qwen3.5-4B checkpoint, released under Apache 2.0, with code under the MIT license. The base model has 32 layers arranged, per Qwen's model card, as eight blocks of three Gated DeltaNet layers and one gated attention layer. Agrawal adds 11 layers in front of those and widens the hidden size so the CPU gets its own dimensions alongside Qwen's.

The CPU implements RV32IM: the base 32-bit RISC-V integer instructions plus multiply and divide. Agrawal says it runs C programs and MicroPython "quite well (although a bit slowly)." His RISC-V design document is more cautious about MicroPython: it says MicroPython runs on the standalone CPU but "not yet inside the merged model," pending a later build.

The practical use he demonstrates is arithmetic. Qwen calls a calc tool using the standard tool-call format, and the call is run by the CPU inside the same forward passes. A small driver called RvChat loads the CPU's firmware and keeps the CPU's trace tokens out of Qwen's own layers.

How do you put a CPU inside a model's weights?

Agrawal's answer has three parts.

Memory from Gated DeltaNet. Qwen3.5 uses Gated DeltaNet, a linear-attention layer whose fixed-size state works as a key-value memory. In the ICLR 2025 paper that introduced it, Songlin Yang, Jan Kautz and Ali Hatamizadeh describe gating as enabling "rapid memory erasure" and the delta rule as allowing "precise memory modifications." Agrawal sets the gate so "nothing ever fades" and uses one-hot keys, vectors with a single 1, so each write overwrites exactly one row and each read retrieves an exact value. His design document says the register file is 32 rows and the RAM is 32 KB, with each row storing one byte as bits.

Arithmetic from feed-forward layers. The design document describes the adder, a five-stage multiplier and a divider built from threshold tests across the MLP layers, with write gates computed so they come out exactly 0 or 1.

A compiler, not training. A compiler turns a circuit description into weights. The model "executes" a program by generating trace tokens: one names the memory row to write (ADDR), the next carries the value (VAL), and a STEP token ends each instruction. The design document reports an average of 1.0 to 1.55 trace tokens per instruction on its C test programs.

The idea that attention-style layers act as writable memory goes back to work Agrawal cites: a 2021 paper by Imanol Schlag, Kazuki Irie and Jürgen Schmidhuber that showed linear attention is formally equivalent to "fast weight" memory systems.

What does "deterministic" mean here?

The word appears in the post's title, but the post doesn't define it. Agrawal's evidence is that he replayed about 230,000 of the CPU's output positions against a reference machine and "found zero mismatches," and that the CPU ran "free-running," meaning it kept going on its own outputs with no reference machine correcting it.

The repository fills in the conditions. Benchmarks use greedy decoding, picking the single most likely token each time rather than sampling. The README says "every value stays exact in bf16," and the example code turns off a reduced-precision matrix-multiply setting to keep results exact. The design document says the circuit's margins absorb small numeric errors, and it records bf16 as "bit-exact on an NVIDIA L4." It also notes that batched runs are "not bit-identical" to single runs at the level of Qwen's internal values, because GPU math rounds differently.

So "deterministic" describes a CPU whose outputs are exact under those settings, not a general property of language models or a guarantee on every GPU and software stack.

What does it show, according to the author?

Last verified: October 29, 2026

On DeepMind's mul_big multiplication set, Agrawal reports 97.5% for Qwenputer against 55% for base Qwen and 100% for Qwen with a Python tool; on NUPA's long-integer arithmetic, 48.6% rising to 100%. Those runs use greedy decoding on 40 problems per set, per the README, so they are small samples. The gains are the same kind a Python tool gives: the README says grade-school word problems (GSM8K, GSM-Hard) end in ties, because "word problems are limited by reasoning rather than arithmetic," and base Qwen stays ahead on long DeepMind expression chains. The KL figure measures how much Qwen's next-token predictions on normal text changed; Agrawal says they stayed within noise.

Agrawal also describes an experimental in-model file store, holding up to 512 files or about 53,000 tokens. In his post, Qwen got facts that changed between chats right 90% of the time with it, against 30% with old chats pasted back in. The README gives a different measure, 83.3 against 7.8 for base Qwen on multi-session recall, without reconciling the two.

What are the limits?

Agrawal lists most of them himself:

• Size: the checkpoint is 18.8 GB, about twice the 9.3 GB base checkpoint the README cites, though he says most of it is zero padding. It runs on one 24 GB GPU. Hugging Face's header for the model shows 9B parameters, more than the 4B in its name.
• Speed: the batched executor runs about 3,200 CPU tokens a second on an Nvidia L4, and each instruction costs decoded tokens, so "a big calculation takes seconds rather than milliseconds." The design document puts a calc call at about 0.5 to 1 second, with Qwen's own text tokens taking most of the time.
• Tooling: the RISC-V model needs the RvChat driver and a custom executor, not plain generate().
• Scope: "It is not a Linux-class chip yet." The design document says control-register writes are illegal and faults halt the CPU; it skips the self-modifying-code and misaligned-access tests.
• Behavior: the README says Qwen "tends to re-verify exact results it has already been given, until it runs out of its token budget."

Hacker News commenters were split between curiosity about how the CPU emulation works and asking what it's for (Tier 3, community reaction).

How does it relate to earlier research?

Compiling programs into transformer weights isn't new. Tracr, by David Lindner and colleagues (NeurIPS 2023), compiles human-readable programs into decoder-only transformers with "known structure," as a test bed for interpretability. "Looped Transformers as Programmable Computers" (ICML 2023), by Angeliki Giannou and colleagues, showed that a transformer with fixed weights, run in a loop, can emulate "a computer using a simple instruction-set architecture," with the input sequence acting as a punch card.

Qwenputer's difference, by Agrawal's account, is that it builds a standard instruction set into a production open-weight model, keeps state in the model's own recurrent memory, and leaves the model's original weights and text behavior intact. His design document says the same compiler was first used for a CHIP-8 machine inside Qwen. None of the papers above is cited in his post apart from Schlag and colleagues; they are context, not his claims. If you're weighing whether an 18.8 GB checkpoint fits on a 24 GB GPU, our small-model memory guide explains the math, and our open-weight licenses comparison covers what Apache 2.0 allows.

What's confirmed, reported and uncertain

• Confirmed (repository, model cards): the code and weights are public; MIT and Apache 2.0 licenses; Qwen3.5-4B's 32-layer Gated DeltaNet layout; the 18.8 GB checkpoint; the documented design (one-hot memory, 32 KB RAM, trace tokens).
• Reported by the author: every test result, including riscv-tests, the 18-million-instruction run, the replay check, speed, arithmetic scores and the KL figure.
• Uncertain: independent replication; whether results hold on other GPUs and software versions; whether MicroPython runs in the merged model today; which filesystem result is the headline one.