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AI chips

AI chips are the processors that train and run AI models: GPUs from Nvidia, AMD and Intel, custom accelerators such as Google's TPUs, and NPUs in PCs. This page tracks the chips themselves, their memory and software, who designs and manufactures them, and the supply limits that decide how many get built.

12 stories · updated Oct 24

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Key facts

Checked Oct 23

NPU requirement for Copilot+ PCs: Many Windows AI features require an NPU that can run at 40+ TOPS
Nvidia Vera Rubin NVL72 in production: Available on CoreWeave's cloud, announced September 30, 2026; CoreWeave says Cognition is the first customer running production workloads on it
Microsoft Maia 300: Detailed October 12, 2026: 288 GB of HBM4 in eight stacks, 18 TB/s of memory bandwidth, compute dies on TSMC N2P; built for LLM inference
Intel GPU D270: Announced October 12, 2026 (GPU D-series, formerly Crescent Island): up to 480 GB of LPDDR5X per card, for AI inference; customer sampling underway
AMD Helion: Introduced October 12, 2026: open rack design with up to 32,768 EPYC CPU cores, or CPU nodes combined with Instinct MI350P GPU nodes; configurations planned for November 2026
TSMC Q3 2026: Reported October 15, 2026: revenue US$46.72 billion (NT$1,494.24 billion); 3nm 33%, 5nm 28%, 2nm 8% and 7nm 10% of wafer revenue
AWS TorchNeuron: Native PyTorch backend for Trainium2 and Trainium3, open source under Apache 2.0; public beta from October 20, 2026
Google TorchTPU: Native PyTorch stack for TPUs, co-developed with Meta's PyTorch team and open source on GitHub under Apache 2.0; Google Cloud announcement dated October 21, 2026
Nvidia DSX POD: Introduced October 21, 2026: containerized Vera Rubin AI factory reference design; partners plan deliveries in early 2027
Nvidia supply-chain capacity: October 21, 2026: substrate capacity for Nvidia products to rise 2.5x over three years; SPIL targets 15x optical-engine capacity for co-packaged optics by mid-2027

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Hardware · NewsNvidia DSX POD and the supply-chain capacity deal: containerized Vera Rubin AI factories, 2.5x substrates and 15x opticsNvidia DSX POD, announced at GTC Berlin on October 21, 2026, is a reference design for Vera Rubin AI factories built in containers, which Nvidia says can be deployed in as little as 14 days at a prepared site. The same day, Nvidia named six suppliers expanding substrate, packaging, testing and optics capacity. What was announced, and what rests on Nvidia's word.Oct 24·5 min read

Policy · NewsNvidia B300 chips on China Telecom's network? What Lava's GPU scan found, and what it doesn't proveNvidia B300 chips reported on China Telecom's network: security firm Lava said on October 22, 2026 that it found 32 Nvidia B300 GPUs reporting through IP addresses geolocated to China. The Information tied them to systems linked to China Telecom. Lava's own post doesn't name the operator and says the finding doesn't establish an export-control violation.Oct 24·5 min read

Developers · CompareTorchTPU vs TorchNeuron: running PyTorch on Google TPUs and AWS Trainium compared (October 2026)TorchTPU vs TorchNeuron: in the same week of October 2026, Google and Amazon open-sourced native PyTorch backends for their AI chips. Both register a new device through PyTorch's PrivateUse1 hook and replace an older PyTorch/XLA path. Here's how they compare on status, chips, PyTorch versions, torch.compile, distributed training and the code you change, per the official docs.Oct 24·9 min read

Latest on AI chips

Policy · NewsNvidia B300 chips on China Telecom's network? What Lava's GPU scan found, and what it doesn't proveNvidia B300 chips reported on China Telecom's network: security firm Lava said on October 22, 2026 that it found 32 Nvidia B300 GPUs reporting through IP addresses geolocated to China. The Information tied them to systems linked to China Telecom. Lava's own post doesn't name the operator and says the finding doesn't establish an export-control violation.Oct 24·5 min read

Developers · CompareTorchTPU vs TorchNeuron: running PyTorch on Google TPUs and AWS Trainium compared (October 2026)TorchTPU vs TorchNeuron: in the same week of October 2026, Google and Amazon open-sourced native PyTorch backends for their AI chips. Both register a new device through PyTorch's PrivateUse1 hook and replace an older PyTorch/XLA path. Here's how they compare on status, chips, PyTorch versions, torch.compile, distributed training and the code you change, per the official docs.Oct 24·Checked Oct 23

Open source · NewsDeepSeek DeepInfer: the Apache 2.0 inference engine behind V4.1 Flash runs on Nvidia Blackwell and Huawei Ascend, with key serving parts held backDeepSeek DeepInfer is the inference engine DeepSeek says serves DeepSeek-V4.1-Flash in production, open-sourced under Apache 2.0 on October 20, 2026. It supports one model on two kinds of hardware, and the KV-cache and load-balancing systems aren't included.Oct 24·5 min read

Hardware · NewsNvidia DSX POD and the supply-chain capacity deal: containerized Vera Rubin AI factories, 2.5x substrates and 15x opticsNvidia DSX POD, announced at GTC Berlin on October 21, 2026, is a reference design for Vera Rubin AI factories built in containers, which Nvidia says can be deployed in as little as 14 days at a prepared site. The same day, Nvidia named six suppliers expanding substrate, packaging, testing and optics capacity. What was announced, and what rests on Nvidia's word.Oct 24·5 min read

Developers · NewsAmazon TorchNeuron: a native PyTorch backend for AWS Trainium, now open source and in public betaAmazon's TorchNeuron lets standard PyTorch code run on AWS Trainium2 and Trainium3 through a native 'neuron' device, replacing the older PyTorch/XLA path. It went into public beta with Neuron 2.33.0 on October 19, 2026, and Amazon open-sourced it on October 20. Here's what changes for developers, per the docs.Oct 20·5 min read

Policy · NewsIs Taiwan making AI chip smuggling to China a crime? What's confirmed about the plan, and what isn'tTaiwan plans to make smuggling AI chips and servers to China a crime by adding them to its Foreign Trade Act controls, but it isn't law yet. What Taiwan's economy ministry has confirmed since June 2026, what Bloomberg reported on October 16, and why prosecutors have had to use forgery charges until now.Oct 18·5 min read

Industry · NewsTSMC Q3 2026 earnings: $46.7 billion in revenue, 2nm at 8% and a 44% growth forecast for the yearTSMC reported third-quarter 2026 revenue of $46.72 billion and record net income of NT$763.06 billion on October 15. HPC made up 68% of revenue, 2nm reached 8% of wafer revenue, Q4 guidance is $52.3–54.3 billion, and 2026 capex stays at $60–64 billion.Oct 16·4 min read

Hardware · NewsIntel GPU D270: Intel's inference GPU trades HBM for up to 480 GB of LPDDR5XAt the OCP Global Summit on October 12, 2026, Intel named its Crescent Island accelerator the GPU D270: an air-cooled 350 W PCIe card with 1.3 petaflops of FP8, 160 GB of LPDDR5X on Intel's own card and up to 480 GB on partner cards. Customer sampling has started; Intel hasn't given a launch date.Oct 14·4 min read

Hardware · NewsMicrosoft Maia 300 AI chip: 288 GB of HBM4, 2nm compute and a 40% tokens-per-megawatt claimOn October 12, 2026, Microsoft unveiled Maia 300, its third in-house AI accelerator, built for inference and due in multi-gigawatt Azure deployments from 2027. The specs, the efficiency claim, and what's still unverified.Oct 13·5 min read

Hardware · NewsAMD Helion: an open rack design for agentic AI with up to 32,768 Zen 6 coresAMD introduced Helion on October 12, 2026, an OCP-based rack blueprint that fills a rack with EPYC 'Venice' CPUs to run AI agents, or mixes in up to 16 Instinct MI350P GPUs. What's in it, who's building it, and when it ships.Oct 13·5 min read

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